module test_sseg;
  reg [3:0] bin_in;
  wire [6:0] segs;
  wire [3:0] bin_out;
  wire valid;
  reg error;
  sseg ss(bin_in,segs);
  invsseg iss(segs, bin_out,valid);
  initial begin
      bin_in=0;error=0;
      repeat (16) begin
	  #100
	  $display("%h %b %h %b",bin_in,segs,bin_out,valid);
	  if(bin_in<10) begin
	      if((bin_in !== bin_out)||(valid !== 0)) begin
		  $display("ERROR:%h %b %h %b",bin_in,segs,bin_out,valid);
		  error = 1;
	      end
	  end
	  else begin
	      if((bin_out!==0)||(valid!==0)) begin
		  $display("ERROR:%h %b %h %b",bin_in,segs,bin_out,valid);
		  error=1;
	      end
	  end
	  bin_in = bin_in+1;
      end
      if(error==0) $display("TEST PASSED");
  end
endmodule


